Scalable low-thermal-budget fabrication of suspended silicon nanowire devices

Silicon nanowires (Si NWs) are versatile one-dimensional building blocks for gas and biochemical sensors, MEMS/NEMS physical transduction platforms, and integrated electronic devices because of their high surface-to-volume ratios and compatibility with semiconductor processing. A key limitation of conventional top-down fabrication is its reliance on furnace-based high-temperature steps, such as thermal oxidation and LPCVD, which can induce residual stress and constrain post-CMOS integration because of thermal-budget limits above 400 °C. Here, we present a furnace-free, low-thermal-budget fabrication approach for suspended Si NWs with a maximum process temperature of 180 °C. The process forms suspended Si NWs at the top surface of both bulk Si substrates and SOI substrates with a 2 µm device layer. The method defines a nanoscale Si surface protrusion and uses a conformal Cr sidewall coating to preserve linewidth during DRIE release. The process yields suspended Si NWs with critical dimensions down to 50 nm, aspect ratios of up to 100, and array pitches of 5 µm, while supporting integration into junctionless field-effect transistor architectures. Electrical measurements confirm ohmic behavior in two-terminal NW devices and demonstrate depletion-mode current modulation in side-gated junctionless FETs, with a threshold voltage of 24 V and approximately 40× current modulation. After nominal 2 nm Pd functionalization, single-NW devices exhibit repeatable 1% H₂ sensing, producing near-complete current suppression of the p-type NW channel at sub-10 nW operating power. By eliminating furnace-based processing, the approach supports post-CMOS-compatible integration, avoids high-temperature stress-inducing process steps, and establishes a scalable platform for suspended Si NW devices.