Versatile van der Waals Step-Barrier Selectors for Cross-Memory Arrays

Cross-point memory arrays offer the minimum 4F2 cell footprint for high-density storage and in-memory computing, but their scalability is fundamentally limited by sneak-path currents unless each memory element is paired with a two-terminal selector that combines ultralow leakage, high drive current, steep turn-on, low operating voltage, high endurance, and thermal stability. Here, a van der Waals (vdW) step-barrier tunneling selector platform is reported, in which semiconductor-insulator-semiconductor energetics are engineered through transition-metal dichalcogenide/h-BN heterostructures and contact selection. Across four heterojunction variants, the platform delivers nonlinearity exceeding 107, OFF-state current densities down to ∼10-9 μA/μm2, ON-state current densities approaching 1 μA/μm2, and low operating voltages, together with weakly temperature-dependent ON-state transport from 80 to 300 K. Accelerated testing at 125 °C verifies endurance of at least 1011 cycles. Monolithic integration with resistive random-access memory yields a uniform 5 × 7 1S1R array, while circuit-level simulations show that 1S1R crossbars maintain a 94.8% read margin and >90% write margin even at the 256 × 256 scale, where selector-free arrays nearly fail. These results demonstrate the effectiveness of vdW step barriers as a selector platform for dense and energy-efficient cross-memory arrays.