Integration of a Two-Terminal Memristor Array with a Vertical Floating-Gate Structure for Antagonistic...

A two-terminal floating-gate memristor can reduce the structural complexity of a three-terminal floating-gate memory by minimizing the number of terminals. However, prior two-terminal memristors with planar floating-gate structures (2TMEM-PFG) exhibited substantial device-to-device variations in I-V characteristics and lacked intrinsic rectification. Here, we demonstrate a two-terminal memristor with a vertical floating-gate structure (2TMEM-VFG) that integrates memristive and self-rectifying functionalities. The 2TMEM-VFG employs a vertically stacked floating-gate (FG) structure, Source/Al2O3/Pt/Al2O3/Drain, reducing the source-drain spacing to 19 nm (TO/FG/BO = 6/5/8 nm) compared with 0.3-10 μm in planar FG devices. This scaling strengthens the electric field across the FG stack, promoting charge tunneling into the FG and yielding a high ON/OFF ratio in memristive switching. The device also exhibits self-rectifying behavior arising from a drain-induced gating effect at the ZnO/Al2O3/metal junction. Integrated in a 16 × 16 crossbar array (256 cells), the 2TMEM-VFG achieves a 91.4% yield with statistically evaluated device-to-device variation, an array-averaged ON/OFF ratio of 537, repeatable switching over 104 cycles, stable operation over thermal (93-333 K) and temporal scales, and ultralow spike current (10-30 pA). In the implementation of a neural network based on a 2TMEM-VFG array to emulate biologically inspired center-surround receptive fields, high device-to-device uniformity enables accurate character classification.