In-Memory Bayesian Machine Using Vertical Cu0.33Te0.67/HfO2/TiN Memristive Crossbar Arrays

Bayesian inference is essential for robust decision-making under uncertainty. However, efficient hardware implementation remains challenging because Bayesian inference requires both a probability representation and repeated probabilistic multiplication with minimal data movement. This work demonstrates an integrated in-memory Bayesian machine using a four-layer vertical Cu0.33Te0.67/HfO2/TiN (v-CTHT) memristive crossbar array. The intrinsic stochastic switching, nonvolatile memory, and self-rectifying behavior of v-CTHT memristors allow prior and likelihood probabilities to be encoded directly as resistance values in page-wise configurations. The posterior probabilities are generated through cascaded interpage NAND and NOT operations within the same vertical array, without external probability-generation circuitry. In contrast to deterministic posterior computation, which generates an identical posterior output even under repeated inference trials for the same input, the proposed method yields a distribution of posterior outputs through intrinsic stochastic switching, enabling stochastic Bayesian inference in memory. The proposed method is experimentally validated at the levels of stochastic device operation, stateful cascaded-AND logic, and page-level probabilistic multiplication. Furthermore, a proof-of-concept protein-folding prediction task is demonstrated through a hardware-informed simulation based on experimentally measured device characteristics. These results establish that probability encoding, storage, and Bayesian inference can be physically unified in a vertical memristive array, providing a compact hardware platform for parallel Bayesian computing.