Opportunities toward Scalable Domain-Wall-Based Spintronic Devices

Since its initial proposal in 2004, racetrack memory, which utilizes current-induced motion of domain walls within a magnetic nanowire, has evolved from a conceptual spintronic device into a mature research platform supported by major advances in materials engineering, nanotechnology, domain-wall physics, and spin-torque mechanisms. Yet, practical racetrack memory or logic remains challenging. The field has entered a new state in which the dominant challenges are no longer associated with driving domain walls or understanding the fundamental mechanisms behind them, but with achieving reliable device operation and fabrication of practical nanoscale devices. Key bottlenecks include the electrical readout of nanoscopic racetrack devices, the integration of magnetic tunnel junctions, the control of stochastic domain-wall behavior, positioning accuracy, and scalability toward three-dimensional (3D) architectures. We briefly summarize the current status of the field and discuss how these challenges redefine research priorities while creating opportunities for advances in electrical readout, 3D device integration, and novel domain-wall-based computing architectures. By highlighting emerging directions in device engineering and advanced characterization, we outline pathways toward translating laboratory-scale demonstrations into scalable, manufacturable spintronic memory and logic technologies.