Design-Space Exploration of Sensing Margin in 1T-nC Ferroelectric Random-Access Memory Considering Capacitor Length...

The rapid advancement of artificial intelligence (AI) necessitates high-performance computing architecture. While compute express link (CXL) technologies facilitate memory expansion, conventional dynamic random-access memory (DRAM) encounters fundamental limitations in power consumption and scalability. Consequently, 1-transistor-n-capacitor (1T-nC) ferroelectric random-access memory (FeRAM) has emerged as a compelling non-volatile candidate; however, process-induced variations substantially degrade its operational reliability. This study investigates the impact of wet etch-induced capacitor length (L_cap) variations and atomic layer deposition (ALD)-induced electrode work function (WF) deviations on the sensing margin of 1T-nC FeRAM. The analysis employs Sentaurus TCAD (Synopsys, Inc., Mountain View, CA, USA, Version T-2022.03) simulations calibrated via the Preisach model, utilizing empirical positive-up-negative-down (PUND) measurements of 7 nm Hf_0.5Zr_0.5O₂ (HZO) capacitors. The results demonstrate that geometric shadowing during wet etching induces non-uniform L_cap profiles. Configuring the bottommost capacitor L_cap to 80 nm secures a sensing margin exceeding the 150 mV DDR4 specification. Furthermore, TiN oxidation during ALD shifts the plate line work function (WF_PL). Constraining WF_PL between 4.51 eV and 4.71 eV at L_cap = 90 nm ensures stable read operations, with this window narrowing further as L_cap is scaled down. By establishing these theoretical boundary conditions, this study provides predictive design guidelines for high-density architectures. Ultimately, mitigating L_cap geometric dispersion and suppressing TiN oxidation are imperative for guaranteeing sufficient sensing margins, thereby advancing scalable, high-density 1T-nC FeRAM solutions for next-generation AI workloads.