Vertical van der Waals Graphene/h-BN/SnS2 Top-Floating-Gate Memory for Optoelectronic Storage and Neuromorphic Computing

Nonvolatile memories based on two-dimensional (2D) van der Waals (vdW) heterostructures have attracted considerable attention because of their atomic-scale thickness, low energy operation, and prolonged data storage capability. However, most reported vdW floating-gate memories employ a bottom-floating-gate configuration, which often leads to a limited on/off ratio due to charge leakage and substrate-induced disturbance. Herein, a top-floating-gate memory based on a graphene (Gr)/h-BN/SnS2 vdW heterostructure is demonstrated, in which the top graphene layer serves as the charge-trapping layer. The device exhibits excellent nonvolatile memory performance, including an on/off ratio of 106, a memory window of 50.8 V, a low standby current of 1 pA, and an extrapolated retention time of 10 years. Owing to the low hole-tunneling barrier between SnS2 and h-BN, the device achieves more than 50 progressively modulated conductance levels under a weak optical pulse of 0.74 nW·mm-2. Moreover, stable long-term potentiation and depression characteristics can be regulated by optical and electrical pulses. Based on these synaptic behaviors, a three-layer multilayer perceptron neural network using the floating-gate memory achieved a classification accuracy of 96% for handwritten digit recognition using the Modified National Institute of Standards and Technology (MNIST) dataset. This work presents a top-floating-gate architecture for 2D-material memories, providing a feasible strategy for future logic-in-memory and neuromorphic computing applications.