A 256-Channel Wireless Neural Recording SoC With Near-Lossless Compression and Robust Bidirectional Telemetry

This paper presents a 256-channel wireless neural-recording system-on-chip (SoC) for wideband acquisition of local field potentials (LFPs) and spikes. The proposed SoC jointly addresses the bottlenecks in data throughput, on-chip data transport, and wireless-link reliability in high-channel-count neural-recording systems. The SoC integrates analog front-ends, distributed neural processors, a low-power tri-state bus, and bidirectional on-off keying (OOK) telemetry. A near-lossless adaptive-delta compressor encodes each 10-bit sample into a fixed-length 4-bit output code. It reduces the uncoded sample payload by 60% while preserving both LFP and spike information. By compressing samples within each analog front-end group before global transfer, the distributed architecture reduces the sample payload carried by the on-chip interconnect. Post-layout simulations show that distributed compression and the proposed tri-state bus reduce bus power by 53.63% and 96.36%, respectively, relative to a centralized APB4-based implementation. The SoC employs a 3.2-GHz uplink and a 433-MHz downlink. A hybrid error-resilience scheme combining convolutional forward-error correction, cyclic redundancy check (CRC)-based error detection, and periodic predictor resynchronization improves the robustness of compressed-data transmission. Fabricated in 65-nm CMOS, the chip occupies 3.54 × 8.18 mm² and consumes 3.49 mW at 30 kHz/ch from a 1.2-V supply while supporting a 44.16 Mbps uplink. These results demonstrate a low-power wireless wideband neural-recording platform with the potential to support freely moving animal experiments.