Heterophase-Engineered Cs3Cu2I5/CsCu2I3 Memristors with Two-Step Resistive Switching
Related Experiment Video
Updated: Nov 7, 2026

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
Published on: May 13, 2020
In Kyu Moon1, Dohwan Jung2, Young Pyo Jeon3
1Department of Chemistry, Hanyang University, Seoul04763, Republic of Korea.
Abstract:
The quest for energy-efficient memory technologies is critically hindered by the performance gap between high-performing but toxic lead-based perovskites and their environmentally benign yet less reliable lead-free counterparts. Here, we address this challenge by engineering the controlled coexistence of crystallographically 0D Cs3Cu2I5 and 1D CsCu2I3 phases using a scalable, hot-air-assisted process. The resulting heterophase architecture produces composition-dependent structural, interfacial, and chemical environments that strongly influence resistive-switching behavior. The optimized devices exhibit a high ON/OFF ratio of up to 7.4 × 108, more than three orders of magnitude higher than that of the corresponding single-phase films, together with electroforming-free operation and a reproducible two-step SET process that provides distinct resistance states for multilevel memory operation. Combined electrical, XPS, cross-sectional STEM/EDS, and post-switching ToF-SIMS analyses support a hybrid valence-change memory/electrochemical metallization (VCM-ECM) filament-evolution framework involving halide-deficient pathways, Cu-O-related oxygen-containing environments, and redistribution of Ag- and Cu-containing species. The two-step SET behavior and two threshold-like regions in the log-log I-V characteristics are consistent with multistage changes in trap occupancy and conductive-path connectivity without requiring direct assignment of the individual transitions to specific vacancy species. These results demonstrate heterophase engineering as an effective materials strategy for regulating local ionic and electronic transport in lead-free halide memristors and provide a pathway toward high-performance, multilevel nonvolatile memory and other ionically active solid-state devices.
Related Concept Videos
MOS Capacitor
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
MOSFET
In an n-MOSFET, the structure includes n-type source and drain...
MOSFET: Enhancement Mode
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no current...
Biasing of Metal-Semiconductor Junctions
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
Biasing of P-N Junction
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...
