Voltage-controlled phosphate precipitation gating in solid-state nanopore memristors

Nanopore arrays create parallel pathways for ion conduction, offering distinct advantages over single-pore geometries. To explore this, we compared a nominally 250 nm diameter single pore with a 3 × 3 SiN_x array matched in total open area, tested in asymmetric CaCl₂/phosphate solutions. Current-voltage hysteresis and pulse responses were characterized across a range of pH values, phosphate concentrations, and scan rates. The array produced gradual current modulation under ±40-80 mV programming and +20 mV read voltages. In 100 mM phosphate, its mean normalized hysteresis area rose from approximately 0.07 to 0.12 across the scan rates examined. Over the first 12 write/read/reset cycles, the array exhibited a read-current drift of 1.4-1.5%, substantially lower than the 11.4-13.3% observed for the single pore under its respective operating protocol. In contrast, the single pore displayed sharper switching transitions and greater sensitivity to the phosphate concentration. These results demonstrate that parallel pore geometries support gradual conductance modulation and markedly reduced drift in cycling records, positioning nanopore arrays as a viable route toward more stable ionic memory elements.