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Related Experiment Videos

A hardware efficient cascadable chip set for ANN's with on-chip backpropagation

T Lehmann1

  • 1Computational Neural Network Center, Technical University of Denmark, Lyngby.

International Journal of Neural Systems
|December 1, 1993
PubMed
Summary

This paper introduces a CMOS chip set for artificial neural networks, enabling on-chip back-propagation learning. This design efficiently supports complex, layered networks without extra wiring or significant circuit additions.

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Area of Science:

  • Artificial Intelligence
  • Computer Engineering
  • Neuroscience

Background:

  • Artificial neural networks (ANNs) require efficient hardware for complex computations.
  • On-chip learning capabilities are crucial for developing sophisticated ANNs.
  • Previous ANN hardware designs often faced limitations in scalability and learning efficiency.

Purpose of the Study:

  • To present an analogue, cascadable CMOS chip set for artificial neural networks.
  • To enable on-chip back-propagation learning in feedforward networks.
  • To demonstrate a hardware solution with minimal circuit overhead and no additional wiring.

Main Methods:

  • Development of a two-chip set: a synapse chip and a neuron chip.
  • Implementation of a fully parallel, layered, feedforward network architecture.

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  • Integration of a back-propagation learning scheme directly onto the chips.

    • Main Results:

    • The chip set supports ANNs of arbitrary size and topology.
    • The learning scheme requires minimal extra circuitry at synapse and neuron sites.
    • No additional wiring is needed for the on-chip learning functionality.

    Conclusions:

    • The presented CMOS chip set offers an efficient and scalable hardware solution for ANNs.
    • On-chip back-propagation learning is achieved with low circuit complexity and no extra wiring.
    • The experimental chip set demonstrates the feasibility of this approach for advanced neural network applications.