Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Experiment Videos

Kakadu--a low power analogue neural network classifier

P H Leong1, M A Jabri

  • 1Department of Electrical Engineering, University of Australia, NSW.

International Journal of Neural Systems
|December 1, 1993
PubMed
Summary

This study presents a low-power analogue neural network VLSI chip with 84 programmable synapses. The chip demonstrates successful training for various classification tasks, achieving high efficiency.

Related Concept Videos

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

STSM 2025 & 2nd African Medical Writing Congress.

La Tunisie medicale·2026
Same author

An overview on the veracity of intraoral digital scanning system and utilization of iTero scanner for analyzing orthodontic study models both <i>In-Vivo</i> and <i>Ex-Vivo</i>.

Nigerian journal of clinical practice·2021
Same author

Anthelmintic activity of Tunisian chamomile (Matricaria recutita L.) against Haemonchus contortus.

Journal of helminthology·2017
Same author

Handwritten digit recognition by adaptive-subspace self-organizing map (ASSOM).

IEEE transactions on neural networks·2008
Same author

Multiresolution forecasting for futures trading using wavelet decompositions.

IEEE transactions on neural networks·2008
Same author

A low-complexity intracardiac electrogram compression algorithm.

IEEE transactions on bio-medical engineering·1999

Area of Science:

  • * Artificial Intelligence and Machine Learning
  • * VLSI (Very Large Scale Integration) Chip Design
  • * Neuromorphic Engineering

Background:

  • * Development of energy-efficient hardware for artificial intelligence is crucial.
  • * Analogue neural networks offer potential for reduced power consumption compared to digital counterparts.
  • * Existing solutions often face challenges in programmability and static weight storage.

Purpose of the Study:

  • * To design and fabricate a low-power analogue neural network VLSI chip.
  • * To implement digitally programmable synapses with static weight storage.
  • * To evaluate the chip's performance on diverse classification tasks.

Main Methods:

  • * Fabrication using a standard 1.2-micron double metal single poly CMOS process.
  • * Integration of 84 synapse elements in 10x6 and 6x4 array configurations.
  • * Digital programmability for synapse weights and static storage for weight retention.

Main Results:

  • * Achieved typical power consumption in the tens of microwatts.
  • * Successfully trained and tested the chip on 4-bit parity recognition.
  • * Demonstrated efficacy in character recognition and intracardiac electrogram signal classification.

Conclusions:

  • * The developed analogue neural network VLSI chip is highly power-efficient.
  • * The chip's programmable synapses and static weight storage enable effective learning.
  • * The technology shows promise for real-world applications in signal processing and pattern recognition.

Related Experiment Videos