On-chip learning with analogue VLSI neural networks

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Neuroscience

Background:

• Analogue VLSI neural networks offer potential for efficient on-chip learning.
• Implementing learning schemes on hardware faces limitations due to analogue precision and noise.
• Weight perturbation is a promising on-chip learning strategy.

Purpose of the Study:

• To evaluate the performance of weight perturbation for analogue VLSI neural networks under realistic hardware constraints.
• To quantify the impact of limited synaptic weight precision on classification accuracy.
• To assess the feasibility of using simplified learning rules in hardware.

Main Methods:

• Simulated weight perturbation learning on analogue VLSI neural network models.
• Incorporated realistic hardware limitations, including synaptic weight precision defined by voltage changes.
• Tested the scheme on a challenging classification task using mobile robot navigation data.
• Compared performance using 8-bit weights with probabilistic updates and a simplified error criterion against 32-bit precision.

Main Results:

• Degradation in classification performance was found to be acceptable under realistic hardware constraints.
• An increase of no more than 7% in error rate was observed for the 8-bit weight configuration compared to 32-bit precision.
• The simplified output error criterion and probabilistic updates did not significantly hinder performance.

Conclusions:

• Weight perturbation is a robust on-chip learning scheme for analogue VLSI neural networks, even with hardware limitations.
• The use of lower-precision weights (e.g., 8-bit) is feasible, enabling more compact and potentially faster hardware implementations.
• This study validates the practical application of weight perturbation in real-world analogue neural network systems.