VLSI neural system architecture for finite ring recursive reduction
Related Experiment Videos
1Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong. dapeng@cs.cityu.edu.hk
Abstract:
The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.
Related Concept Videos
Block Diagram Reduction
The first step in this process is the identification and relocation of a branch point. A branch point, where a...
Woodward–Hoffmann Selection Rules and Microscopic Reversibility
Synthetic Disvision of Polynomials
Rationalizing Substitutions
Linear Approximation in Frequency Domain
In contrast, nonlinear systems do not inherently possess these properties. However, for small deviations around an operating point, a nonlinear system can often be approximated as linear.
Network Function of a Circuit