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Related Experiment Videos

An advanced demultiplexing system for physiological stimulation

K E Jones1, R A Normann

  • 1Department of Bioengineering, University of Utah, Salt Lake City 84112, USA.

IEEE Transactions on Bio-Medical Engineering
|December 24, 1997
PubMed
Summary
This summary is machine-generated.

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A new integrated circuit chip reduces data transmission for controlling intracortical stimulating electrode arrays. This advanced chip enables high-density neural stimulation with significantly lower data rates, improving system efficiency.

Area of Science:

  • Biomedical Engineering
  • Neurotechnology
  • Integrated Circuit Design

Background:

  • Intracortical stimulating electrode arrays require complex signal multiplexing/demultiplexing.
  • Radio telemetry in neural stimulation systems can limit data transmission rates.
  • Efficient control of high-density electrode arrays is crucial for advanced applications.

Purpose of the Study:

  • To design and implement a CMOS very large scale integration (VLSI) chip for efficient control of intracortical stimulating electrode arrays.
  • To reduce the data transmission rate required for operating large-scale neural stimulators.
  • To enable simultaneous stimulation of multiple channels with reduced control overhead.

Main Methods:

  • Developed a novel scheme for multiplexing/demultiplexing stimulation signals.

Related Experiment Videos

  • Incorporated on-chip multiple current sources for simultaneous stimulation.
  • Integrated on-chip timers and RAM to manage stimulus amplitude and pulse timing.
  • Designed a scalable architecture implemented as an eight-channel stimulator, expandable to 625 channels.

    • Main Results:

    • Achieved significant reduction in digital information transmission for controlling numerous electrodes.
    • Reduced control data by up to fourfold through on-chip timers.
    • Further reduced data rates by five to ten times or more using on-chip RAM for stimulus parameter storage.
    • Demonstrated scalability to a 625-channel stimulator with data rates below 2 Mbps.

    Conclusions:

    • The designed CMOS VLSI chip effectively reduces data transmission requirements for high-density intracortical stimulation.
    • On-chip integration of current sources, timers, and RAM enhances efficiency and scalability.
    • This architecture is suitable for advanced neuroprosthetics and research requiring precise, high-channel-count neural stimulation.