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Discover Nano|April 2, 2025
Design of a gate-all-around arch-shaped tunnel-field-effect-transistor-based capacitorless DRAMSeung Ji Bae, Sang Ho Lee, Jin Park, et al.
Journal of Nanoscience and Nanotechnology|January 5, 2016
Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed OperationsYoung Jun Yoon, Hye Rim Eun, Jae Hwa Seo, et al.
Discover Nano|February 10, 2025
Novel three-dimensional stacked capacitorless DRAM architecture using partially etched nanosheets for high-density memory applicationsMin Seok Kim, Sang Ho Lee, Jin Park, et al.
Journal of Nanoscience and Nanotechnology|May 12, 2015
Design and analysis of vertical-channel gallium nitride (GaN) junctionless nanowire transistors (JNT)Jae Hwa Seo, Young Jun Yoon, Hwan Gi Lee, et al.
Nanomaterials (Basel, Switzerland)|March 12, 2024
Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film TransistorsJeong-Hyeon Na, Jun-Hyeong Park, Won Park, et al.
Journal of Nanoscience and Nanotechnology|July 27, 2016
Nonlinear Transport in Organic Thin Film Transistors with Soluble Small Molecule SemiconductorHyeok Kim, Dong-Seok Song, Jin-Hyuk Kwon, et al.
Nanomaterials (Basel, Switzerland)|October 14, 2022
Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped StructureHee Dae An, Sang Ho Lee, Jin Park, et al.
Nanomaterials (Basel, Switzerland)|July 14, 2023
Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain BoundariesJin Park, Sang-Ho Lee, Ga-Eon Kang, et al.
Materials (Basel, Switzerland)|February 15, 2022
Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub> Dual-Layer InsulatorSo-Ra Min, Min-Su Cho, Sang-Ho Lee, et al.
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