Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Peng Suo

2PUBLICATIONS
4CO-AUTHORS
Electrical circuits and systemsElectrical energy generation (incl. renewables, excl. photovoltaics)
Featured researcher

Get your video featured.

JoVEPublish with JoVE
Featured researcher

Get your video featured.

JoVEPublish with JoVE
Journal

Publications (2)

Sort by Publication Date:
|Jun 17, 2025
Gate-Controlled Ultrafast Interlayer Carrier Flow in Gr/MoS<sub>2</sub> Heterostructures.

Chen Wang, Yu Chen, Peng Suo

|Mar 06, 2025
Revealing a Nonlinear Photocurrent in the Graphene/MoS<sub>2</sub> Heterostructure via Terahertz Emission Spectroscopy.

Yifan Cheng, Xian Lin, Chunwei Wang

Pageof 1

Frequent Collaborators

2 joint publications

Guohong Ma

1 joint publications

Zeyu Zhang

1 joint publications

Juan Du

1 joint publications

Weimin Liu

Frequent Collaborators

2 joint publications

Guohong Ma

1 joint publications

Zeyu Zhang

1 joint publications

Juan Du

1 joint publications

Weimin Liu

Top Related Videos

Optimized Fabrication Procedure for High-Quality Graphene-based Moir&#233; Superlattice Devices
11:24

Optimized Fabrication Procedure for High-Quality Graphene-based Moir&#233; Superlattice Devices

Published on : Jul 11, 2025

6.6K
Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
11:42

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Published on : Jul 24, 2015

15.4K
See more related videos

Top Related Videos

Optimized Fabrication Procedure for High-Quality Graphene-based Moir&#233; Superlattice Devices
11:24

Optimized Fabrication Procedure for High-Quality Graphene-based Moir&#233; Superlattice Devices

Published on : Jul 11, 2025

6.6K
Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
11:42

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Published on : Jul 24, 2015

15.4K
See more related videos