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Transistores de efecto de campo de fuente Dirac como interruptores electrónicos de alto rendimiento y eficiencia
Chenguang Qiu1, Fei Liu2, Lin Xu1
1Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China.
Science (New York, N.Y.)
|June 16, 2018
Resumen
Los investigadores desarrollaron un transistor de efecto de campo de fuente Dirac de grafeno (DS-FET) que reduce significativamente el consumo de energía en la electrónica. Este nuevo transistor logra un balanceo por debajo del umbral de 60mV / década, superando una limitación clave en los transistores convencionales.
Área de la Ciencia:
- Ciencias de los materiales
- Física de los semiconductores
- La nanoelectrónica
Sus antecedentes:
- La reducción del consumo de energía en los dispositivos electrónicos es crucial.
- Los transistores de efecto de campo (FET) están limitados por una oscilación subumbral (SS) de 60mV/década debido al límite térmico.
- Bajar el voltaje de alimentación es clave para reducir la potencia, pero SS lo limita.
Objetivo del estudio:
- Para superar el límite de oscilación subumbral de 60mV/década en las FET.
- Para demostrar un nuevo diseño de transistores para un menor consumo de energía.
- Explorar el uso de fuentes de grafeno Dirac para mejorar el rendimiento del transistor.
Principales métodos:
- Fabricación de un transistor de efecto de campo de fuente Dirac de grafeno (DS-FET).
- Utilizó un canal de nanotubos de carbono dentro de la arquitectura DS-FET.
- El rendimiento del dispositivo caracterizado, incluido el balanceo por debajo del umbral (SS) y los niveles de corriente a temperatura ambiente.
Principales resultados:
- Logró un SS promedio de 40mV/década durante cuatro décadas de corriente.
- Se ha demostrado que la corriente del dispositivo es alta (I60 hasta 40 microamperios por micrómetro) a 60 mV/década.
- Realizó una corriente en estado similar a las FET de silicio de última generación, pero a un voltaje de alimentación más bajo (0,5 V frente a 0,7 V).
- Se observó un SS fuera de estado más pronunciado por debajo de 35mV/década en comparación con los FET de silicio.
Conclusiones:
- Los FET de fuente de grafeno Dirac ofrecen una vía viable para reducir significativamente los voltajes de funcionamiento y el consumo de energía.
- El diseño de DS-FET supera el límite convencional de SS, lo que permite una electrónica más eficiente desde el punto de vista energético.
- Esta tecnología presenta una alternativa prometedora a los FET de silicio para dispositivos de baja potencia de próxima generación.
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