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Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
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Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
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Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
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The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) plays a pivotal role in modern electronics thanks to its versatility and efficiency in controlling electrical currents. This device, also known as IGFET, MISFET, and MOSFET, has three main terminals: the Source, Drain, and Gate. MOSFETs are classified into n-channel or p-channel types based on the doping characteristics of their substrate and the source or drain regions.
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Diseño de lógica ternaria basado en nuevos transistores de efecto de campo de deriva-túnel

Bin Lu1,2, Hua Qiang1, Dawei Wang1

  • 1School of Physics and Information Engineering, Shanxi Normal University, Taiyuan 030031, China.

Nanomaterials (Basel, Switzerland)
|August 27, 2025
PubMed
Resumen

Un nuevo transistor de efecto de campo de deriva de túnel (TDDFET) permite circuitos lógicos ternários eficientes. Este nuevo diseño de dispositivo y su integración en HSPICE son cruciales para el avance de la investigación de computación ternaria.

Palabras clave:
Circuitos lógicos ternales combinadosMecanismo de conducción híbridocircuitos lógicos ternales secuencialesInvertidor ternario

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Área de la Ciencia:

  • Física de los dispositivos de semiconductores
  • Diseño lógico digital
  • La electrónica cuántica

Sus antecedentes:

  • La lógica ternaria ofrece ventajas sobre la lógica binaria para ciertas tareas computacionales.
  • Las implementaciones de lógica ternaria existentes se enfrentan a desafíos en cuanto a eficiencia y escalabilidad.
  • Se necesitan nuevas estructuras de transistores para realizar circuitos ternários de alto rendimiento.

Objetivo del estudio:

  • Proponer y analizar un nuevo transistor de efecto de campo de deriva de túnel (TDDFET).
  • Demostrar la viabilidad de los TDDFET para el diseño de circuitos lógicos ternales.
  • Establecer una base para el desarrollo avanzado de sistemas de lógica ternaria.

Principales métodos:

  • Análisis detallado del principio de funcionamiento del TDDFET.
  • Modelado del dispositivo "caja negra" utilizando el método de búsqueda de tablas.
  • Integración del entorno de simulación HSPICE a través del lenguaje Verilog-A.

Principales resultados:

  • Diseño exitoso de puertas lógicas ternales básicas: STI, NTI, PTI, T-NAND, T-NOR.
  • Implementación de circuitos ternales combinados: T-Encoder, T-Decoder y T-HA.
  • Desarrollo de circuitos ternários secuenciales: T-D-Latch, T-DFF.

Conclusiones:

  • El TDDFET propuesto es un componente viable para circuitos lógicos ternários.
  • Los modelos de simulación desarrollados facilitan una mayor investigación y desarrollo en computación ternaria.
  • Este trabajo contribuye significativamente a la investigación de sistemas lógicos ternales avanzados.