中間層 エンジニアリングされたフェロ電気NANDフラッシュ 次世代高密度ストレージシステムの信頼性と安定性のボトルネックを克服する
Giuk Kim1, Sangho Lee1, Hyojun Choi1
1Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.
Advanced science (Weinheim, Baden-Wurttemberg, Germany)
|August 23, 2025
まとめ
エンジニアリングゲートスタックを備えたフェロ電気トランジスタは,3D NANDフラッシュメモリの信頼性と安定性を向上させます. この進歩により,性能が向上し,次世代の非揮発性ストレージに より高いビット密度を可能にします.
科学分野:
- 材料科学
- 電気工学
- 半導体物理学
背景:
- フェロ電気トランジスタは,多層貯蔵と低圧操作により,次世代の非揮発性メモリの鍵です.
- ゲート注入型のフェロ電気トランジスタは,3D NANDフラッシュに優位性がありますが,複雑な偏振スイッチとチャージトラッピングの相互作用により信頼性が妨げられます.
研究 の 目的:
- ゲートスタックを設計することで 鉄電 NAND の信頼性と安定性の問題を解決します
- ポラライゼーションダイナミクスを調節し,ポラライゼーションスイッチングとチャージトラッピングメカニズムのカップリングを改善します.
主な方法:
- HfZrOxマトリックス内の中間層を持つゲートスタックエンジニアリング.
- ゲートスタック最適化とデバイス物理を理解するための分析モデリング.
主要な成果:
- メモリーウィンドウは11Vまで,動作電圧は18V以下.
- 10年以上のトリプルレベル細胞保持,干渉免疫,および54%の値電圧の変動が示されました.
- プログラム電圧を20%削減し,攻撃的な垂直スケーリングと25%高いビット密度を可能にします.
結論:
- エンジニアリングされたゲートスタックは,フェロエレクトリックNANDの信頼性と安定性のボトルネックを克服します.
- フェロエレクトリックNANDは,高度な非揮発性メモリのためのスケーラブルでエネルギー効率の高いソリューションです.
- この研究は,将来のメモリアプリケーションのためのフェロ電気ゲートスタックを最適化するための洞察を提供します.
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