FPGA アプリケーションでデバイスのパフォーマンスを向上させるためのステップ・スペーサー FinFET 設計
Meysam Zareiee1, Mahsa Mehrad2, Abdulkarim Tawfik2
1Department of Design, Manufacturing and Engineering Management, University of Strathclyde, Glasgow G1 1XQ, UK.
Micromachines
|August 28, 2025
まとめ
新しいステップ・スペーサー・ストラクチャード・フィンフェット (S3-FinFET) は,静電制御を改善し,トランジスタの漏れ電流を減少させます. この設計は,高度なフィールドプログラム可能なゲート配列 (FPGA) に最適であり,電力効率と速度を向上させます.
科学分野:
- 半導体装置の物理
- 先進的なトランジスタアーキテクチャ
- ナノスケール電子
背景:
- 従来のMOSFETは,短チャンネル効果とゲート漏れのために10nm以下のスケールで制限に直面しています.
- FinFETは,特に SOIのジャンクションレス・バリエーションは,スケールされたノードのための強化された静電制御を提供します.
- 近代的な統合回路の要求を満たすために,改良されたトランジスタ設計が必要である.
研究 の 目的:
- 新しいステップ・スペーサー・ストラクチャード・フィンフェット (S3-FinFET) を提案し,評価する.
- 先進的なシミュレーション技術を用いてS3-FinFETの性能向上を調査する.
- フィールドプログラム可能なゲート配列 (FPGA) のようなアプリケーションに対するS3-FinFETの適性を評価する.
主な方法:
- 3層のHfO2/Si3N4/HfO2スペーサーを備えた新しいS3-FinFETアーキテクチャの開発.
- デバイスの評価のために2D技術コンピュータ・アイド・デザイン (TCAD) のシミュレーションを使用する.
- トランスファー/アウトプット特性,オン/オフ比率,サブスレッジスイング (SS),ドレイン誘導のバリアダウン (DIBL) を含む主要な性能指標の分析.
主要な成果:
- S3-FinFETは静電制御を大幅に改善し,寄生虫効果を減少させました.
- 主要な性能指標は,漏れ電流抑制と高周波動作の大幅な改善を示しています.
- シミュレーションは,従来の設計と比較して,優れているサブスレッジスイング (SS) とドレイン誘発のバリアダウン (DIBL) を示しています.
結論:
- S3-FinFETアーキテクチャは,深層スケールトランジスタの限界を克服するための有望なソリューションを提供します.
- 提案された設計は,効率的で高速な電子アプリケーションに不可欠な性能特性を備えています.
- S3-FinFETは,高速化と信号完全性により,フィールドプログラム可能なゲート配列 (FPGA) に特に適しています.
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