熱ラジカル活性化によるSiO₂のスケーラブルな等方性原子層エッチング

Wafer scale atomic layer etching (ALE), one of the key fabrication processes of both cutting-edge gate-all-around (GAA) and complementary field-effect transistors, is essential for the implementation of a 3D gate stack where a few nanometer-thick gate oxide should be etched out in an isotropic manner. In the present study, we successfully resolved the limit of conventional thermal ALE, which has been using excessively reactive and corrosive HF, by adopting plasma-assisted thermal ALE with SF₆ for the source of fluorine radicals. As a result, we successfully established self-limiting etching conditions and, in turn, an optimized ALE in a 6 in. wafer scale with a uniformity of more than 99% at 5 Torr. We suggested a step-by-step ALE mechanism of surface oxide layers consisting of conversion by trimethylaluminum, fluorination by F*, and removal, which was supported by the combination of an alternative fluorination reaction and X-ray photoelectron spectroscopy analysis. After the fabrication of silicon GAA multichannel nanostructure, deposition of SiO₂ by ALD, and applying the optimized ALE, we confirmed that the oxide layers are conformally etched out from cross-sectional transmission electron microscopy.