在FPGAs上进行分布式大规模图形处理
Amin Sahebi1,2, Marco Barbone3, Marco Procaccini1,4
1Department of Information Engineering and Mathematics, University of Siena, Siena, Italy.
概括
这项研究引入了一种新的现场可编程门阵列 (FPGA) 框架,用于加速大规模图形处理. 该系统高效地处理数据传输,超过了复杂图形算法的CPU和GPU解决方案.
科学领域:
- 计算机科学 计算机科学
- 硬件加速器 硬件加速器
- 高性能计算 高性能计算
背景情况:
- 由于不规则的内存访问模式,大规模的图形处理面临挑战,导致CPU和GPU的性能下降.
- 现场可编程网关数组 (FPGA) 提供并行处理功能,但受到芯片内存的限制,导致数据传输瓶.
- 高效的图形分区和分布式多FPGA架构对于克服资源限制和改善数据局部性至关重要.
研究的目的:
- 提出一个 FPGA 处理引擎,可以重叠和定制数据传输,以充分利用 FPGA.
- 将这个引擎集成到FPGA集群的框架中,使得使用离线分区能够高效地分发大规模图形.
- 在超出单个设备内存容量的大规模数据集上展示高性能图形处理.
主要方法:
- 开发了一种旨在重叠,隐藏和定制数据传输的FPGA处理引擎.
- 将引擎集成到使用FPGA集群和离线分区方法进行图形分布的框架中.
- 利用Hadoop进行更高层次的图形映射和数据分布到FPGA层.
主要成果:
- 拟议的FPGA解决方案实现了PageRank等图形算法的显著加快,超过了最先进的CPU和GPU实现.
- 对于大尺度图形,FPGA解决方案表现出卓越的性能,与CPU (12x) 相比,其速度是26倍,并克服了GPU内存限制.
- 与其他FPGA解决方案相比,提出的方法是28倍快,而多FPGA系统提供了额外的12倍的性能改进.
结论:
- 图形分区与拟议的FPGA架构相结合,为数百万顶点和数十亿边缘的图形提供高性能.
- 该框架有效地解决了FPGA有限的芯片内存的挑战,通过优化数据传输和实现分布式处理.
- 这项研究强调了FPGA对大型数据集的实施效率,显示了它在下一代图形处理加速方面的潜力.
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