相关实验视频
Updated: Jul 24, 2025

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Preparation of Neuronal Co-cultures with Single Cell Precision
Published on: May 20, 2014
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在神经形芯片中实现高核心神经元密度,通过区域,功耗和数据访问带宽之间的权衡
IEEE transactions on biomedical circuits and systems
|July 5, 2023
概括
这项研究介绍了神经形态芯片的在芯片上和离芯片共设计,优化了内存使用. 这种方法可以显著降低功耗,并提高神经元密度,用于先进的人工智能应用.
科学领域:
- 神经形态工程的神经形态工程
- 集成电路设计 集成电路设计
- 人工智能 硬件 硬件
背景情况:
- 神经形态芯片中的芯片内存消耗大量资源,限制了神经元密度.
- 离芯片内存引入了电力消耗和数据访问瓶.
研究的目的:
- 为神经形态芯片提出一个在芯片上和离芯片上的共同设计方法.
- 为优化芯片面积,功率和数据访问带宽开发一个优点图 (FOM).
- 增强神经元密度,减少神经形态系统中的功耗.
主要方法:
- 开发了一个优点数字 (FOM) 来评估设计的权衡.
- 采用深度多重复合和重量共享技术.
- 实现了混合内存设计,以优化芯片内外内存分布.
主要成果:
- 在基于FOM的基线设计上实现了1.085×的改进.
- 芯片内存储压力降低了92.88%,总功率降低了27.86%.
- 制造了一个10核的神经形态芯片,核心神经元密度为4.92K/mm2,3.3930.56×的改进.
结论:
- 共同设计方法有效地平衡了芯片面积,功耗和数据访问带宽.
- 开发的神经形态芯片显示了SNN应用的高密度和效率.
- 这项工作为创造高密度,大规模的神经形态芯片提供了可行的策略.
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