一个基于OpenCL的FPGA加速器,用于更快的R-CNNN
Jianjing An1,2, Dezheng Zhang1,2, Ke Xu1,2
1Institute of Information Science, Beijing Jiaotong University, Beijing 100044, China.
Entropy (Basel, Switzerland)
|July 8, 2023
概括
这项研究引入了一种新的FPGA加速器,用于更快的R-CNN对象检测,显著提高性能. 硬件和软件的共同设计实现了比现有的Faster R-CNN加速器提高10倍的吞吐量.
科学领域:
- 计算机工程 计算机工程
- 人工智能的人工智能
- 硬件加速器 硬件加速器
背景情况:
- 基于卷积神经网络 (CNN) 的对象检测算法,特别是Faster R-CNN,由于高计算和内存复杂性而面临挑战.
- 现有的硬件加速器设计主要集中在像YOLO这样的单阶段探测器上,留下了一个有效的更快的R-CNN实现的空白.
- 现场可编程网关数组 (FPGA) 为复杂的深度学习模型的定制硬件加速提供了一个有前途的平台.
研究的目的:
- 提出一个软硬件共同设计方案,用于在使用OpenCL的FPGA上实现更快的R-CNN对象检测算法.
- 设计一个高效的,深层管道的FPGA硬件加速器,能够支持Faster R-CNN的各种骨干网络.
- 通过固定点定量化和层融合等技术优化Faster R-CNN算法用于硬件实现.
主要方法:
- 开发一个深管道FPGA硬件加速器,为快速R-CNN量身定制.
- 实现硬件意识的软件算法,包括固定点定量化,层融合和多批次感兴趣区域 (RoIs) 探测器.
- 利用OpenCL进行软硬件共同设计,并设计一个端到端的空间探索方案,用于性能和资源评估.
主要成果:
- 拟议的FPGA加速器在172 MHz的工作频率下实现了846.9 GOP/s的峰值吞吐量.
- 与最先进的Faster R-CNN加速器相比,演示了10倍的推断吞吐量改进.
- 实现了2.1倍的推断吞吐量改进,而不是一个阶段的YOLO加速器.
结论:
- 拟议的软硬件联合设计方案有效地解决了FPGAs上的Faster R-CNN的计算和内存挑战.
- 开发的FPGA加速器提供了显著的性能提升,使其成为实时对象检测的竞争性解决方案.
- 这项工作推动了复杂的深度学习模型的硬件加速领域的发展,特别是对于双阶段对象检测器.
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