在FPGA上为10Gbps以太网提供双队列结构的低延迟TOE

Dan Yang1, Xuhan Xu1, Tianyang Chen1

  • 1Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China.

PubMed
概括

本研究介绍了一种基于FPGA的新型硬件卸载引擎,具有双队列存储结构,以增强TCP/IP处理. 新设计显著降低了延迟,并改善了对高需求数据中心网络的吞吐量.

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