一个大小,重量,功率和成本效益高的32通道时间到数字转换器,使用一种新的波形联合方法.
Saleh M Alshahry1, Awwad H Alshehry1, Abdullah K Alhazmi1
1Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, OH 45469, USA.
Sensors (Basel, Switzerland)
|July 29, 2023
概括
本研究介绍了一种低成本,高精度的时间到数字转换器 (TDC),使用FPGA上的新型Wave Union类型A (WU-A) 架构. 它以最小的尺寸,重量,功率和成本 (SWaP-C) 实现了卓越的性能.
科学领域:
- 电子和电气工程 电子和电气工程
- 数字信号处理 数字信号处理
- 仪器仪表和测量仪器的使用
背景情况:
- 高精度的时间间隔测量对于各种应用至关重要.
- 现有的时间到数字转换器 (TDC) 经常面临尺寸,重量,功率和成本 (SWaP-C) 的挑战.
- 现场可编程门阵列 (FPGA) 提供了一个灵活的平台来实现复杂的数字系统.
研究的目的:
- 开发一个高精度,多通道的时间到数字转换器 (TDC),低SWaP-C要求.
- 引入一种新的Wave Union类型A (WU-A) 架构,以实现高效的TDC实现.
- 提出一种自动校准算法,以提高TDC性能.
主要方法:
- 在低成本的Xilinx Artix-7 FPGA上实施基于Tapped Delay Line (TDL) 的TDC.
- 开发一种新的WU-A架构,使用单个多重处理器来产生脉冲列车.
- 集成自动校准算法以减轻差异非线性 (DNL) 和积分非线性 (INL).
主要成果:
- 实现了平均时间精度低于3皮秒 (ps).
- 演示了大约1.81 ps的根平均平方 (RMS) 分辨率.
- 与之前的工作相比,拟议的多通道TDC显示了最低的SWaP-C要求.
结论:
- 在FPGA上的新WU-A TDC架构为高精度时间间隔测量提供了高效的解决方案.
- 开发的TDC符合严格的低SWaP-C要求,使其适合各种应用.
- 自动校准算法有效地提高了TDC线性和整体性能.
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