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基于FPGA的动态可配置数据包解析器的设计
Ying Sun1,2, Zhichuan Guo1,2
1National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.
Micromachines
|August 26, 2023
概括
我们为可编程网络开发了一个动态的,低延迟的FPGA解析器,克服了传统解析器的局限性. 这种可适应的解决方案实现了高吞吐量和最小的延迟,以实现高效的网络数据处理.
科学领域:
- 计算机工程 计算机工程
- 网络架构 网络架构
- 硬件加速器 硬件加速器
背景情况:
- 传统的固定类型协议解析器很难满足现代可编程网络的动态需求.
- 现有的解决方案往往面临着延迟和配置能力的限制,阻碍了网络灵活性.
研究的目的:
- 提出一个动态和可配置的低延迟解析器,在现场可编程网关数组 (FPGA) 上实现.
- 通过解决传统协议解析器的局限性来提高网络的适应性和效率.
主要方法:
- 设计了一个FPGA架构,包括三个协议分析模块和TCAM-SRAM,以实现高效的数据处理.
- 优化状态机器和并行提取匹配以减少延迟.
- 引入了链接映射和容器概念,以灵活制定规则和增强解析器可扩展性,通过软件定义网络 (SDN) 实现动态配置.
主要成果:
- 在Xilinx超大尺度+FPGA上实现了超过80 Gbps的吞吐量.
- 在Layer 4 (L4) 协议解析中显示的最大延迟仅为36纳秒.
- 使用基于 cocotb 的框架验证和模拟设计.
结论:
- 提出的动态FPGA解析器为可编程网络提供了低延迟,高吞吐量解决方案.
- 该架构通过动态SDN控制提供灵活适应各种网络场景.
- 这种方法显著改善了传统的固定类型协议解析器的局限性.
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