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基于晶片的,,化薄体 (5纳米) 双门MOSFET用于混合射频应用的参数分析
Pattunnarajam Paramasivam1, Naveenbalaji Gowthaman2, Viranjay M Srivastava2
1Department of Electronics and Communication Engineering, Prince Shri Venkateshwara Padmavathy Engineering College, Chennai, 600127, India.
Recent patents on nanotechnology
|September 19, 2023
概括
这项研究分析了2纳米长度的印化 (In-GaAs) 双门 (DG) MOSFET,证明了先进的CMOS设备的减少泄漏电流. 优化的设计提高了未来纳米技术和混合射频应用的性能.
科学领域:
- 半导体物理 半导体物理
- 材料科学 材料科学 材料科学
- 电气工程 电气工程
背景情况:
- 对基于晶圆的高性能印化 (In-GaAs) n型双门 (DG) MOSFET进行分析,门长为2 nm.
- 在混合射频应用中研究结构特征和设备参数之间的关系,例如开关电流比率 (ION/IOFF) 和传导率 (Gm).
研究的目的:
- 为了分析一个新的DG MOSFET架构的电气行为.
- 优化设备参数以提高射频应用中的性能.
- 探索高级CMOS和纳米技术应用的潜力.
主要方法:
- 在300K时使用非平衡绿色函数 (NEGF) 机制,用于DG MOSFET模拟.
- 采用La2O3作为门介电,其等效氧化物厚度 (EOT) 为1nm,源排气装置长度 (LSD) 为45nm.
- 应用费米 - 迪拉克统计学来建模半导体 - 绝缘体接口上的电荷分布.
主要成果:
- 实现了4.52mA的最大排水电流 (IDmax) 和18.3×107的出色的开启/关闭开关电流比 (ION/IOFF).
- 获得了关键性能指标,包括最大电流密度 (Jmax) 为52.4μA/m2,电子流动性 (μn) 为1417cm2V-1S-1,和透导率 (Gm) 为3140μS/μm.
- 使用NEGF形式主义,对电子密度和子频段能量配置文件进行了有效控制.
结论:
- 拟议的GD MOSFET设计显示出明显减少的泄漏电流.
- 这种设计非常适合先进的基于的固态CMOS设备和微电子.
- 该技术对纳米技术中的未来一代设备应用具有前景.
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