由高性能原子层沉积的ZnO薄膜晶体管启用的CMOS后端兼容的内存阵列和逻辑电路
Wenhui Wang1, Ke Li1, Jun Lan1
1School of Microelectronics, Southern University of Science and Technology, 518055, Shenzhen, China.
Nature communications
|September 28, 2023
概括
高性能氧化 (ZnO) 薄膜晶体管 (TFT) 是使用原子层沉积 (ALD) 开发的. 这些ZnO TFT实现了记录流动性,并为先进的3D集成电路提供了功能1T1R阵列.
科学领域:
- 材料科学 材料科学 材料科学
- 电气工程 电气工程
- 纳米技术纳米技术
背景情况:
- 推进3D集成电路 (IC) 的非常大规模集成 (VLSI) 需要在补充性金属氧化物半导体 (CMOS) 后端线 (BEOL) 中使用高性能晶体管.
- 氧化 (ZnO) 的原子层沉积 (ALD) 提供了一个有前途的解决方案,因为其有利的电气特性和低加工温度与铜互连相兼容.
研究的目的:
- 开发和优化ALD沉积的ZnO薄膜晶体管 (TFT) 用于单体3DIC应用.
- 将ZnO TFT与电阻随机存储器 (RRAM) 集成,并开发一个与SPICE兼容的电路共设计模型.
主要方法:
- 优化原子层沉积 (ALD) 用于 ZnO 薄膜晶体管制造.
- 在1kbit (32x32) 1T1R数组中将ZnO TFT与HfO2 RRAM集成.
- 为ZnO TFTs开发一个与SPICE兼容的模型,并模拟电路设计.
主要成果:
- 在ALD沉积的ZnO TFT中实现了85/140cm2/V·s的创纪录的场效应和内在移动性 (μFE /μo).
- 在集成ZnO TFTs的1T1R数组中展示了成功的RRAM切换功能.
- 设计并经过实验验证的基于ZnO TFT的逆变器和5级环振荡器,其工作频率超过10MHz.
结论:
- 优化的ALD ZnO TFT适用于单体3DIC中的高性能BEOL应用.
- 开发的SPICE模型为未来高性能集成电路的共同设计提供了便利.
- ZnO TFT显示了在下一代电子设备中实现高级内存和逻辑功能的潜力.
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