从延迟线路增加可址的超导体集成电路内存
Jennifer Volk1,2, Alex Wynn3, Evan Golden3
1Department of Electrical and Computer Engineering, UC Santa Barbara, Santa Barbara, CA, 93106, USA. jevolk@ucsb.edu.
Scientific reports
|October 3, 2023
概括
超导延迟线内存为节能计算提供了一个可扩展的解决方案. 这种新的方法使用被动传输线来实现高级处理器的高数据密度和最小的控制电路.
科学领域:
- 固态物理 固态物理
- 电气工程 电气工程 电气工程
- 计算机科学 计算机科学
背景情况:
- 超导体电子正在为节能计算和量子控制重新审视.
- 可扩展的超导存储器仍然是一个重大的技术挑战.
- 现有的方法主要集中在存储细胞的小型化上.
研究的目的:
- 介绍一种新的超导延迟线记忆系统,作为细胞小型化的替代方案.
- 为了利用超导被动传输线路的特性,用于内存应用.
- 开发一个可扩展和节能的超导存储器解决方案.
主要方法:
- 利用超导被动传输线路的最小衰减和分散.
- 设计一个完全超导的延迟线内存架构.
- 使用麻省理工学院林肯实验室SC2制造工艺.
主要成果:
- 已证明的数据密度为每平方厘米 (Mbit/cm2) 的几十兆比特.
- 实现了20至100 GHz之间的运行速度.
- 显示 ±24% 和 ±13% 的偏差边缘.
- 循环设计允许最小的控制电路,并消除了数据分割/合并.
结论:
- 超导延迟线内存系统为可扩展的超导内存提供了一个有希望的替代方案.
- 这种设计使得可以廉价实现顺序访问和内容可定位的内存.
- 未来的制造工艺进步表明,数据密度可能达到数百兆比特/平方厘米,甚至更高.
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