高速度和节能非同步携带前增量器
Padmanabhan Balasubramanian1, Weichen Liu1
1School of Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore.
PloS one
|October 5, 2023
概括
这项研究引入了新的非同步的 carry-look-ahead加法器 (CLAs),以实现更快,更节能的计算. 区块CLA (BCLA) 设计显著优化了性能指标,如延迟,面积和功耗.
科学领域:
- 计算机工程 计算机工程
- 数字电路设计数字电路设计
- 在 VLSI 设计中,
背景情况:
- 加法是处理器中一个关键的算术操作.
- 高速和高能效的加热器设计对于实际应用至关重要.
- 异步设计在速度和功率方面提供了潜在的优势.
研究的目的:
- 设计和评估新型异步携带前增量器 (CLA).
- 为了比较标准CLA (SCLA) 和块CLA (BCLA) 的性能.
- 优化添加器设计以减少循环时间,面积,功率和能源消耗.
主要方法:
- 使用RZH和ROH协议开发单调,双轨编码的CLA.
- 使用28纳米CMOS工艺技术实现.
- 拟议的SCLA和BCLA与最先进的异步加法器的性能比较.
主要成果:
- 拟议的BCLA显示出与SCLA相比的显著改善.
- 对于一个32位的添加,BCLA实现了高达32.6%的循环时间,29%的面积,4.3%的功率和35.5%的能量 (RZH) 的减少.
- 与其他异步加法器相比,BCLA还显示了周期时间和功率/能量的减少.
结论:
- 与SCLA和现有设计相比,新型异步BCLA提供了更高的性能.
- 拟议的BCLA是高速和节能数字处理的有希望的解决方案.
- 异步添加器,特别是BCLA,是提高处理器效率的关键.
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