一种灵活的芯片上系统可编程的门阵列架构,用于原型化实验性全球导航卫星系统接收器
Marc Majoral1, Carles Fernández-Prades1, Javier Arribas1
1Centre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), Parc Mediterrani de la Tecnologia-Building B4, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, Spain.
Sensors (Basel, Switzerland)
|December 9, 2023
概括
研究人员开发了一种低成本的System-on-Chip Field-Programmable Gate Array (SoC-FPGA) 架构,用于快速原型化全球导航卫星系统 (GNSS) 接收器. 这种灵活的设计允许使用实时信号测试新的GNSS功能.
科学领域:
- 电气工程 电气工程
- 计算机工程 计算机工程
- 航空航天工程 航空航天工程
背景情况:
- 全球导航卫星系统 (GNSS) 技术正在迅速发展,需要敏捷的研发工具.
- 越来越复杂的GNSS集成电路 (IC) 限制了研究人员修改或检查接收器内部的能力.
- 现有的原型制造方法可能缺乏尖端GNSS研究所需的灵活性或效率.
研究的目的:
- 为实验性GNSS接收器原型设计设计和展示一个低成本的System-on-Chip Field-Programmable Gate Array (SoC-FPGA) 架构.
- 为了使紧的,便携式的,多通道的,多星座的GNSS接收器的发展.
- 为使用实时信号测试新型和非标准GNSS功能提供灵活的平台.
主要方法:
- 开发了一种系统在芯片上的可编程现场网关阵列 (SoC-FPGA) 架构.
- 集成软件定义无线电 (SDR) 技术与FPGA能效.
- 设计和评估一个通用GNSS接收器作为研究试验台.
主要成果:
- 证明了在静态和低地球轨道 (LEO) 场景中获取和跟踪GNSS信号的能力.
- 评估了导航可观测的质量.
- 评估了从原型接收器获得的导航解决方案的准确性.
结论:
- 拟议的SoC-FPGA架构为先进GNSS接收器的原型设计提供了灵活和高效的解决方案.
- 开发的试验台接收器成功获取和跟踪GNSS信号,验证其研究应用的性能.
- 这种方法有助于探索创新的GNSS功能和系统设计.
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