氧化物半导体异质连接晶体管具有负差传导率,用于多值逻辑电路
Jong Chan Shin1, Jae Hak Lee2,3, Minho Jin2
1Department of Chemical and Biological Engineering, and Institute of Chemical Processes, College of Engineering, Seoul National University, Seoul 08826, Republic of Korea.
ACS nano
|January 4, 2024
概括
本研究引入了一种新型的氧化物半导体异质连接晶体管,采用常规的CMOS工艺,使用负差传导率 (NDT),使多值逻辑 (MVL) 电路能够实现更高的数据密度和更低的功耗.
科学领域:
- 半导体物理 半导体物理
- 材料科学 材料科学 材料科学
- 电子工程 电子工程
背景情况:
- 多值逻辑 (MVL) 技术在数据密度和功率效率方面比传统的补充金属氧化物半导体 (CMOS) 技术具有优势.
- 负差传导率 (NDT) 的异质连接晶体管 (TR) 对MVL电路至关重要,但通常使用与CMOS过程不兼容的材料.
研究的目的:
- 开发一种具有NDT特征的氧化物半导体 (OS) 异联晶体管,与传统CMOS制造相兼容.
- 为了证明在MVL电路中使用这种晶体管的可行性.
主要方法:
- 使用p型铜I) 氧化物 (Cu2O) 和n型氧化 (IGZO) 制造异质连接晶体管.
- 电气性能的表征,包括开/关比,无线测试范围和峰值-谷流比 (PVCR).
- 通过改变设备几何和层厚度来分析设备操作,并演示三元逆变器.
主要成果:
- 制造的OS异质连接TR表现出高的开/关比 (∼3×103),广泛的NDT范围 (∼29V),以及高的PVCR (≈25).
- 在多个制造的设备中证实了统一的设备性能.
- 一个三元逆变器展示了三个不同的逻辑状态,由于设备的NDT特性,错误率得到了改善.
结论:
- 开发的具有NDT特性的氧化物半导体异质连接晶体管与传统的CMOS工艺兼容.
- 这项技术通过增强数据密度和降低功耗,显示了推动MVL电路的巨大潜力.
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