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相关概念视频

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

779
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
779

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相关实验视频

Updated: Jul 6, 2025

Fabrication of Silica Ultra High Quality Factor Microresonators
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基于定向逻辑和微环共振器的超紧型光学全.

Feng Chen, Shenghang Zhou, Yuhong Xia

    Applied optics
    |January 4, 2024
    PubMed
    概括

    我们使用定向逻辑和微环共振器开发了一种超紧的光学全增子器,大大减少了先进光学计算系统的组件数量和足迹.

    科学领域:

    • 光子学是指光子学的使用方法.
    • 光学计算是指光学计算的应用.
    • 集成电路 集成电路

    背景情况:

    • 紧的光子集成电路 (PIC) 对光学计算至关重要.
    • 由于当前光学设计中组件数量很高,因此阻碍了密集的集成.

    研究的目的:

    • 提出一个超紧的光学全.
    • 为了减少光学元件的数量和整体足迹.

    主要方法:

    • 在电路设计中使用定向逻辑和微环共振器.
    • 使用有限差异时间域 (FDTD) 模拟进行验证.

    主要成果:

    • 拟议的光学全达到了59.2μm × 29.2μm的最小足迹.
    • 显示最大延迟时间约为10ps,可实现100 GHz的数据速率.

    结论:

    • 与现有解决方案相比,拟议的设计可显著减少组件数量和尺寸.
    • FDTD模拟证实了超紧的光学全器对于高速光学计算应用的有效性和可行性.

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