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Updated: Jul 5, 2025

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics

Published on: September 28, 2016

在一个改进的4H-SiC VDMOSFET中,对无式感应切换进行了二维计算机辅助设计研究

Xinfeng Nie¹, Ying Wang¹, Chenghao Yu¹

¹Key Laboratory of RF Circuits and Systems, Ministry of Education, Hangzhou Dianzi University, Hangzhou 310018, China.

|January 23, 2024

概括

这项研究引入了一种改进的碳化 (SiC) 垂直双扩散 MOSFET (VDMOSFET),其表现出优异的无感应开关 (UIS) 性能和较低的启动阻力,与传统设计相比. 这些发现为高雪崩可靠性应用提供了宝贵的见解.

科学领域:

材料科学材料科学材料科学
电气工程电气工程
半导体物理半导体物理

背景情况:

碳化 (SiC) 金属氧化物半导体场效应晶体管 (MOSFET) 对于高功率工业应用至关重要,因为它们具有出色的热和电性能.
雪崩故障是SiC MOSFET在苛刻的操作环境中的可靠性问题.
现有的VDMOSFET设计需要改进,以满足严格的雪崩可靠性标准.

研究的目的:

提出和评估一个改进的SiC VDMOSFET设计,以提高雪崩性.
为了比较拟议的设备与传统的缓冲层VDMOSFET (B-VDMOSFET) 的无式感应开关 (UIS) 性能.
为了评估修改后的VDMOSFET的电阻特性.

主要方法:

使用Sentaurus TCAD模拟软件与混合模式模拟器来构建一个未紧的感应开关 (UIS) 测试电路.
进行了详细的模拟,以分析在UIS压力下的拟议和传统SiC VDMOSFET的行为.
评估设备性能指标,包括UIS能力和特定的电阻 (R_on,sp).

主要成果:

在相同的测试条件下,与B-VDMOSFET相比,改进的SiC VDMOSFET表现出明显更好的UIS性能.
模拟表明,修改后的VDMOSFET在室温下比B-VDMOSFET.实现了较低的特定电阻 (R_on,sp).
拟议的设计有效地减轻了SiC电源设备的雪崩故障问题.

结论:

开发的SiC VDMOSFET设计为要求高雪崩可靠性的应用提供了有前途的解决方案.
模拟结果验证了改进的设备的增强UIS性能和改进的电阻.
这项研究为开发强大的SiC VDMOSFET用于具有挑战性的工业场景提供了关键的参考.

关键词:

2D数值模拟 2D数值模拟如果是SiC SiC 在UISIS中,使用的是UISIS.雪崩是一场雪崩.电源 MOSFET 的使用情况.

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