基于逻辑解决的方法,用于有效的可靠性分析
Zhengguang Tang1, Cong Li1, Hailong You1
1School of Microelectronics, Xidian University, Xi'an 710071, China.
Micromachines
|January 23, 2024
概括
这项研究引入了一种改进的方法来分析数字电路的老化效应,提高准确性和速度. 它解决了设备老化的依赖性,以防止性能下降并确保可靠性.
科学领域:
- 电气工程 电气工程
- 计算机工程 计算机工程
- 材料科学 材料科学 材料科学
背景情况:
- 深度纳米级CMOS技术的扩展加剧了设备老化效应,降低了电路性能,并可能导致功能故障.
- 可靠性意识的电路分析对于评估老化的影响至关重要,但现有的方法忽视了设备老化的依赖性,导致不准确的退化评估.
- 精确的应力分析对于预测和减轻现代集成电路老化的影响至关重要.
研究的目的:
- 为可靠性意识的静态定时分析提出改进的分析方法,以考虑设备老化依赖.
- 为了提高数字电路中衰老路径延迟评估的准确性.
- 为了减少衰老时间评估中的悲观主义,并尽量减少衰老意识合成流中的性能牺牲.
主要方法:
- 建议采用逻辑解析的改进分析方法来解决设备老化依赖.
- 该方法的重点是提高可靠性意识的静态时间分析的准确性.
- 实验验证将拟议的方法与传统策略和精确的SPICE模拟进行比较.
主要成果:
- 与传统策略相比,拟议的方法在评估衰老路径延迟方面表现出更高的准确性.
- 过度悲观的衰老时间评估是减少的.
- 与SPICE模拟相比,只有0.56%的相对误差实现了显著的378倍加速度.
- 在老化意识的合成流中,电路性能牺牲是减少的.
结论:
- 拟议的分析方法显著提高了深纳米级CMOS电路的可靠性意识静态定时分析的准确性和效率.
- 通过考虑设备老化的依赖性,该方法提供了更可靠的降解评估,并减少了悲观情绪.
- 高效率和精度使该方法适用于大规模的数字电路可靠性分析,满足速度需求,同时保持晶体管级模拟精度.
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