相关实验视频
Updated: Apr 9, 2026

10:39
Reconfigurable Microfluidic Channel with Pin-discretized Sidewalls
Published on: April 12, 2018
7.5K
一个新道准备方案,以优化三维NAND闪存内存中的程序干扰
Kaikai You1, Lei Jin1,2, Jianquan Jia1
1Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.
Micromachines
|February 24, 2024
概括
这项研究引入了"Gate诱导排水泄漏 (GIDL) 预充电",以提高3D NAND闪存的可靠性. 这种方法通过增强频道潜力而没有结构变化来抑制节目干扰.
科学领域:
- 电气工程 电气工程
- 半导体设备物理 半导体设备物理
- 材料科学 材料科学 材料科学
背景情况:
- 三维 (3D) 垂直NAND闪存由于程序干扰而面临可靠性挑战.
- 没有选择的词线 (WL) 的狭窄的操作电压窗口加剧了福勒-诺德海姆 (FN) 道.
- 对程序和受阻字符串的矛盾电压要求使干扰抑制复杂化.
研究的目的:
- 在3D NAND中研究通道电位和电子密度之间的关系.
- 开发一种用于减轻3D NAND闪存中的程序干扰的新方法.
- 为了提高3D NAND设备的可靠性和操作窗口.
主要方法:
- 对通道潜力和电子密度动态的系统分析.
- 引入一个"门引起的排水泄漏 (GIDL) 预付费"计划.
- 使用技术计算机辅助设计 (TCAD) 模拟和真实数据进行验证.
主要成果:
- 通过利用产生的孔,GIDL预充电方法有效地提高了未选择的通道潜力.
- 在3D NAND设备中观察到明显抑制的程序干扰.
- 在不改变设备结构或操作电压的情况下,证明了更大的通道干扰窗口.
结论:
- GIDL预充技术为3D NAND中的程序干扰提供了一个可行的解决方案.
- 这种方法提高了可靠性,而不需要新的制造工艺或修改操作参数.
- 这些发现为更强大,更可靠的NAND闪存提供了途径.
更多相关视频
07:23Fabrication of Nanoheight Channels Incorporating Surface Acoustic Wave Actuation via Lithium Niobate for Acoustic Nanofluidics
Published on: February 5, 2020
5.8K
09:49In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
Published on: May 13, 2020
4.1K
相关概念视频
Biasing of P-N Junction
2.7K
The operation of a p-n junction diode involves various biasing conditions, including forward bias, reverse bias, and equilibrium.
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...
2.7K
Design Example: Capacitance Multiplier Circuit
1.8K
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
1.8K
MOSFET: Enhancement Mode
1.0K
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
1.0K