基于分布式算术对称的二维块有限脉冲响应波器架构的实施
Pratyusha Chowdari Ch1, J B Seventline2
1Department of Electronics and Communications Engineering, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, 500090, India.
F1000Research
|March 5, 2024
概括
本研究介绍了一种高效的2D FIR过器,使用块处理和对称性,显著减少功率和面积. 新型架构优化乘数和内存,以提高固定系数应用中的性能.
科学领域:
- 数字信号处理 数字信号处理
- 在 VLSI 设计中,
- 过器架构 的架构.
背景情况:
- 在各种信号处理应用中,高效地实现二维 (2-D) 有限冲动响应 (FIR) 过器至关重要.
- 现有的架构在优化面积,功耗和吞吐量方面经常面临挑战.
- 利用过系数对称性可以减少硬件复杂性.
研究的目的:
- 提出和实施高效的2D FIR过架构,利用区块处理和利用过系数对称性 (对角和象限).
- 为了减少乘数的数量,并优化内存使用,以提高面积和功率效率.
- 与现有方法相比,评估拟议架构的性能.
主要方法:
- 开发2D FIR波器架构,包括区块处理,以提高吞吐量.
- 利用基于分布式算法 (DA) 的乘法与基于双端口内存的查找表 (DP-MLUT) 来最大限度地减少面积和功率.
- 使用Verilog HDL和45nm技术的合成实现,性能分析包括面积,延迟和功耗.
主要成果:
- 与现有设计相比,拟议的架构显示了功率,面积,面积延迟产品 (ADP) 和功率延迟产品 (PDP) 的显著改进.
- 区块大小为4的2D区块象限对称过器 (QSF) 实现了功率降低58.94%,面积降低59.5%,ADP降低48.44%,PDP降低47.78%.
- 采用了内存再利用和共享技术,以减少寄存器数量和电路复杂性.
结论:
- 一个新的,面积和功率高效的基于DA的具有对称性的2D块FIR过器架构已经成功实现.
- 整合对称和基于DP-LUT的乘法器有效地将硬件资源降到最低.
- 拟议的过器架构非常适合需要固定过系数的应用,因为它的效率很高.
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