随机计算 卷积神经网络架构 重新发明用于在现场可编程门数组上的高效人工智能工作负载
Yang Yang Lee1, Zaini Abdul Halim1, Mohd Nadhir Ab Wahab2
1School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Nibong Tebal, 14300 Penang, Malaysia.
Research (Washington, D.C.)
|March 5, 2024
概括
本研究介绍了用于人工智能 (AI) 边缘计算的FPGA高效随机计算 (SC) 架构,为卷积神经网络 (CNN) 实现了显著的节能和更高的吞吐量. 虽然对分类有效,但SC是有效的.
科学领域:
- 计算机工程 计算机工程
- 人工智能的人工智能
- 硬件加速器 硬件加速器
背景情况:
- 随机计算 (SC) 对ASIC上的AI边缘计算进行了充分研究,特别是对于CNN.
- 对FPGAs的SC优化缺乏,阻碍了高效的缩放和位流聚合.
- 现有的SC方法在FPGA实施和性能扩展方面面临挑战.
研究的目的:
- 开发具有FPGA效率的8位SC CNN计算架构.
- 在Kintex7 FPGA上使用新的SC设计实现完全并行的CNN模型.
- 评估拟议的SC CNN在FPGA上的性能,准确性和能源效率.
主要方法:
- 重新发明了FPGA高效的SC架构:SC多重复合器多次积累,多次积累函数生成器,以及二进制整形线性单元.
- 在Kintex7 FPGA上实现完全并行的CNN模型.
- 与二进制计算相比,对精度,节能和数据吞吐量进行评估.
主要成果:
- 与二进制计算相比,在MNIST分类任务上实现了最小的准确性损失 (0.14%).
- 已证明,每张图像的前至少节省了99.72%的能量.
- 获得了比现代硬件高出31倍的数据吞吐量.
- 早期决策终止可以实现指数级的性能增长,而准确性损失微不足道.
结论:
- 具有FPGA效率的SC CNN对AI边缘计算非常有希望,特别是在分类任务中.
- 拟议的SC硬件可大大节省能源,提高吞吐量.
- SC固有的噪声限制了它对回归任务的适用性,使其不适合此类应用.
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