基于低功耗和面积高效的memristor的非挥发性D锁和翻盘:设计和分析
Haroon Rasheed S1, Rajeev Pankaj Nelapati1
1School of Electronics Engineering, Vellore Institute of Technology, Vellore, Tamilnadu, India.
PloS one
|March 7, 2024
概括
这项研究引入了一种使用memristor比分逻辑 (MRL) 和CMOS组件的新型非挥发性锁. 这种基于memristor的设计为高级内存应用提供了更低的功耗和更小的面积.
科学领域:
- 电气工程 电气工程
- 计算机工程 计算机工程
- 材料科学 材料科学 材料科学
背景情况:
- 非易失性存储元件对于下一代存储至关重要,与传统闪存相比,它们具有优势.
- 记忆器是有希望的不易挥发的元素,适合于基本的序列逻辑电路,如锁和翻转.
- 现有的非挥发性内存解决方案通常面临功耗,速度或耐久性方面的限制.
研究的目的:
- 设计和模拟一个紧的,低压的,可靠的非挥发性锁架构.
- 为了集成memristors与CMOS组件用于增强的内存应用程序.
- 评估基于memristor的设计与现有的非挥发性拓的性能.
主要方法:
- 使用Verilog-A模型开发一个memristor元件.
- 一个非易失性锁架构的设计,采用memristor比例逻辑 (MRL) 逆变器和CMOS.
- 对拟议设计的功率,面积,能量和编程时间与其他非挥发性电路进行模拟和比较.
主要成果:
- 基于memristor的非挥发性锁设计经过模拟验证,证明了紧性,低压操作和可靠性.
- 该架构扩展到主-奴隶翻转机,成功配置为计数器和变速寄存器.
- 与类似的非易失性设计相比,拟议的非易失性锁实现了24%的功耗减少和近10%的面积减少.
结论:
- 开发的基于memristor的非挥发性锁架构有效地存储数据,证实其非挥发性.
- 整合memristors为内存应用提供了显著的功率效率和设备足迹的显著改进.
- 这种基于memristor的方法为未来的高性能,低功耗非挥发性内存系统提供了可行的替代方案.
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