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优化FPGA高精度混乱系统的实施,以提高性能
Issam Damaj1, Ashraf Zaher2, Wafic Lawand3
1Department of Engineering, Cardiff School of Technologies, Cardiff Metropolitan University, Cardiff, United Kingdom.
PloS one
|April 9, 2024
概括
本研究介绍了用于混乱系统的高速现场可编程门阵列 (FPGA) 内核,实现安全通信和数据加密应用的高吞吐量和精度.
科学领域:
- 混乱系统的数字硬件实现.
- 现场可编程门阵列 (FPGA) 核心开发.
背景情况:
- 混乱的芯片系统为安全通信,数据加密和随机数生成提供了巨大的潜力.
- 混乱系统的数字实现需要在速度,复杂性和精度方面提供高性能.
研究的目的:
- 为混乱系统,特别是洛伦兹系统开发高速FPGA核心.
- 用高精度来实现第六阶混乱方程的数值集成技术.
主要方法:
- 开发了FPGA核心,使用混乱系统的数值集成技术.
- 根据算法复杂度,精度,硬件面积,吞吐量,功耗和运行频率分析和评估核心.
- 通过模拟和与现有文献进行比较来验证设计.
主要成果:
- 实现了高效的第六级洛伦茨离散,吞吐量为3.39Gbps,精度为16位.
- 获得了21.17 Gbps的吞吐量,用于第一阶段实施,具有64位精度.
- 证明了超越类似调查的基准绩效.
结论:
- 成功创建了用于混乱系统的高性能FPGA核心.
- 开发的核心提供了卓越的吞吐量和精度,在该领域树立了新的基准.
- 这些进步对于下一代安全的通信和数据处理系统至关重要.
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