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相关实验视频

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混合精度浮点 (HPFP) 选择优化硬件受限加速器的CNN培训.

Muhammad Junaid1, Hayotjon Aliev1, SangBo Park1

  • 1Department of Electronics, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju 28644, Republic of Korea.

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概括

本研究介绍了边缘设备上AI加速器的混合精度浮点 (HPFP) 算法. 通过优化数据精度,HPFP可降低能源消耗和内存访问,从而实现高效的深度神经网络训练,以最小的准确性损失.

关键词:
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科学领域:

  • 人工智能的人工智能
  • 计算机架构 计算机架构
  • 硬件加速器 硬件加速器

背景情况:

  • 边缘设备需要高效的AI加速器,因为浮点操作的硬件成本很高.
  • 像MSFP和FlexBlock这样的传统块浮点 (BFP) 格式的动态范围和精度有限,阻碍了深度神经网络 (DNN) 训练.
  • 现有的低精度格式经常使用FP32进行积累,限制了硬件节省.

研究的目的:

  • 引入混合精度 (HPFP) 选择算法,以解决AI加速器中传统浮点格式的局限性.
  • 为了平衡层级的算术运算和数据路径精度,在边缘设备上进行高效的DNN训练.
  • 通过在减少的浮点格式中执行所有乘法和积累操作,实现显著的硬件节省.

主要方法:

  • 开发了HPFP选择算法,用于系统的精度降低和混合精度策略.
  • 为YOLOv2-Tiny使用不同的混合精度策略实施了两个训练加速器.
  • 比较HPFP与传统的Bfloat16加速器进行比较.

主要成果:

  • 使用10位数据路径和12位用于更高精度层的HPFP实现了49.4%的能源消耗降低.
  • 通过HPFP方法,记忆访问减少了37.5%.
  • 与Bfloat16相比,观察到0.8%的边际平均精度 (mAP) 降解.

结论:

  • 拟议的HPFP选择算法允许对边缘设备进行紧,低功耗的AI加速器的高效设计.
  • HPFP提供了一种可行的解决方案,可以降低硬件成本和能源消耗,而不会显著地降低精度.
  • 这种方法有助于在资源有限的边缘设备上进行有效的DNN培训.