一个基于FPGA的全精度低功率CNN加速器,具有可重新配置的结构
1School of Electronics and Information Technology (School of Microelectronics), Sun Yat-sen University, Guangzhou 510275, China.
Sensors (Basel, Switzerland)
|April 13, 2024
概括
本研究介绍了一种新的卷积神经网络 (CNN) 加速器,用于电力受限制的环境. 该设计实现了高吞吐量和显著的功率效率,用于在FPGA上完全精确的CNN.
科学领域:
- 计算机工程 计算机工程
- 人工智能的人工智能
- 硬件加速器 硬件加速器
背景情况:
- 卷积神经网络 (CNN) 提供了显著的进步,但在低功耗应用程序的计算需求和功耗方面面临挑战.
- 现有的CNN加速器,通常基于高级合成 (HLS),在高效的现场可编程门阵列 (FPGA) 资源利用和完全精确的计算方面扎.
研究的目的:
- 开发一个专门的CNN加速器,解决当前方法的局限性,使在电力有限的环境中实现高效部署.
- 提高FPGA计算资源的利用率,并支持完全精确的CNN.
主要方法:
- 整合矢量点乘积来统一卷积和完全连接的层,使用特征图的行矢量作为处理单元.
- 开发一个准确的设计空间探索 (DSE) 模型,以优化每个CNN层的设计点.
- 实现动态部分重新配置以最大限度地提高每个层的资源访问.
主要成果:
- 在 7A100T 和 ZU15EG 平台上,实现了平均卷积层吞吐量为 28.985 GOP/s 和 246.711 GOP/s,达到完全精度.
- 证明了显著的功率效率提高,与最先进的FPGA实现相比,最大收益为23.989x和15.376x.
- 通过成功实施AlexNet和VGG16来验证该方法.
结论:
- 拟议的统一加速器设计有效地平衡了延迟和资源消耗,同时消除了数据重新排列的开销.
- DSE模型和动态部分重新配置使各种CNN架构的性能和资源利用得以优化.
- 这项工作在FPGAs上的节能,高性能CNN加速方面取得了重大进展.
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