具有薄膜异构结构的二维道化记忆晶体管用于低功率逻辑内存辅助金属氧化物半导体
Taoyu Zou1, Seongmin Heo1, Gwon Byeon1
1Department of Chemical Engineering, Pohang University of Science and Technology, 77 Cheongam-Ro, Nam-Gu, Pohang 37673, Republic of Korea.
ACS nano
|May 15, 2024
概括
研究人员使用MoS2和WSe2.2开发了新的2D半导体道化记忆晶体管. 这些设备通过操纵缺陷和屏障高度来实现低功耗的内存逻辑应用.
科学领域:
- 材料科学 材料科学 材料科学
- 纳米科学是一个纳米科学.
- 固态物理 固态物理
背景情况:
- 对高性能,微型半导体设备的日益增长的需求推动了电子材料的创新.
- 由于其原子薄结构,二维 (2D) 半导体为先进电子提供了独特的特性.
研究的目的:
- 开发使用二维半导体异构结构的新型道化晶体管.
- 调查缺陷和屏障高度调制在设备功能中的作用.
- 为了展示低功耗的内存逻辑设备.
主要方法:
- 使用二维二硫化物 (MoS2) 和二维二硫化物 (WSe2) 制造薄膜异构结构.
- 异质连接屏障高度的门调节和通过溶液过程对内在缺陷的操纵.
- 对WSe2纳米片进行电化学剥离,以研究缺陷类型.
主要成果:
- 成功实现了双调和内存操作的道化晶体管.
- 在WSe2.2中识别广泛的边缘缺陷和四种特定缺陷类型 (单空位,二空位,空位, adatoms).
- 构建基于金属氧化物半导体 (CMOS) 的互补逻辑内存设备.
结论:
- 开发的2D道化晶体管表现出了下一代纳米电子技术有前途的特性.
- 这些设备在皮卡瓦特范围内实现了超低的静电消耗.
- 缺陷工程和障碍高度调制是用于高级2D设备功能的有效策略.
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