DAM SRAM CORE:一个高效的高速和低功耗的CIM SRAM CORE设计,用于二进制神经网络中的特征提取卷积层
Ruiyong Zhao1,2, Zhenghui Gong1, Yulan Liu1,2
1Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200031, China.
Micromachines
|May 25, 2024
概括
本研究介绍了DAM SRAM CORE,这是用于内存计算的11T SRAM单元,可实现高效的并行乘积运算. 它显著降低了功耗,并提高了AI硬件应用的准确性.
科学领域:
- 电气工程 电气工程
- 计算机架构 计算机架构
- 人工智能 硬件 硬件
背景情况:
- 在内存计算架构对于克服·诺伊曼瓶在人工智能等数据密集型应用程序中至关重要.
- 现有的SRAM设计往往面临在存储单元中有效集成计算能力的局限性.
- 在内存层面,对低功耗,高性能计算解决方案的需求越来越大.
研究的目的:
- 提出并验证一种新的11T SRAM单元设计,即DAM SRAM CORE,用于高效的内存计算.
- 在单个SRAM单元中集成存储和计算,用于大规模并行多倍积累 (MAC) 操作.
- 为了提高面积效率,降低功耗,并提高基于SRAM的AI加速器的计算精度.
主要方法:
- 一个统一的11T SRAM单元的设计,集成存储和计算.
- 实现基于aXNOR的动态计算模式,以减少功耗.
- 整合了自稳定电压梯度量化电路,以提高精度.
- 使用55nmCMOS逻辑过程和基于模拟的验证制造64x64位DAM SRAM CORE.
主要成果:
- DAM SRAM CORE在SRAM阵列中展示了高效的并行MAC操作.
- 实现了0.48mW/mm2的低静态功耗和11.367mW/mm2.2的计算功耗.
- 提供5位输出结果与1位输入和权重数据,展示了高精度.
- 实现了109.75 GOPS的数据吞吐量和21.95 TOPS/W的能源效率.
结论:
- 拟议的DAM SRAM CORE为内存计算提供了一个紧且面积高效的解决方案.
- 动态aXNOR计算模式和量子化电路显著提高了性能和准确性,同时降低了功率.
- 制造和模拟的核心验证了新设计对低功耗,高通量AI应用程序的有效性.
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