通过在三 FinFET 上使用介电容度等级的堆叠氧化物来减少离电和泄漏电流:TCAD研究:一项TCAD研究
Alper Ülkü1,2, Esin Uçar1,2, Ramis Berkay Serin1,2
1Department of Material Science and Engineering, Gebze Technical University, Kocaeli 41400, Türkiye.
Micromachines
|June 27, 2024
概括
研究人员为FinFET晶体管开发了新的门介电堆,大大减少了状态下排水电流和门泄漏. 这一创新为下一代纳米电子提供了一条通往更好的集成和更低功耗的道路.
科学领域:
- 半导体物理 半导体物理
- 材料科学 材料科学 材料科学
- 纳米电子学纳米电子学
背景情况:
- 金属氧化物半导体场效应晶体管 (MOSFET) 演变为具有垂直包裹通道的3D FinFET.
- 包括翅膀宽度 (Wfin) 和门氧化物宽度 (tox) 在内的FinFET尺寸已经接近了石版画的极限.
- 扩大规模的挑战需要新的方法来进一步改进设备.
研究的目的:
- 为了研究使用多阶段, κ级堆叠门介电器的FinFETs的性能提升.
- 探索 Penn 模型和 Maxwell-Garnett 公式在纳米层材料中计算介电常数的应用.
- 为了证明介电电容性匹配和k-分级对先进的纳米电子设备的潜力.
主要方法:
- 调整了佩恩模型和麦克斯韦-加内特混合公式,用于介电常数 (κ) 的计算.
- 模拟的FinFET使用两级和三级 κ级堆叠门介电器 (SiO2,Si3N4,Al2O3,HfO2,La2O3,TiO2).
- 与单层介电器对应器的性能比较.
主要成果:
- 与 κ 分级门氧化物配合的 FinFET 与单层介电材料相比显示出更高的性能.
- 通过Al2O3组合,实现了异常状态排水电流 (IOFF) 的显著减少,降至6.45 × 10-15 A:TiO2.
- 将门泄漏电流 (IG) 减少到2.04 × 10-11 A,使用Al2O3:HfO2:La2O3组合.
- 在1 nm以下的极限处,已证明有效的介电层层.
结论:
- κ级门介电材料为克服当前FinFET扩展限制提供了一个有希望的策略.
- 介电电容性匹配和k-分级对于提高设备性能至关重要.
- 这种方法为下一代纳米电子技术铺平了道路,具有更高的集成性和更低的功耗.
相关概念视频
Characteristics of MOSFET
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Metal-oxide-semiconductor field-effect Transistors, or MOSFETs, play a critical role in electronic circuits. They are primarily utilized for amplifying and switching signals.
Various vital parameters influence their functionality, which is crucial for theory and electronics applications. First, channel dimensions, precisely length, and width, are pivotal. The size of these channels affects the transistor's ability to carry current and switching speeds; shorter channels typically enable...
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