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Updated: Apr 8, 2026

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

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偏差频率对自下而上SiO2空隙填充的作用,使用等离子增强原子层沉积

Ye Ji Shin1, Ho Gon Kim1, Seung Yup Choi1

  • 1Department of Advanced Materials and Science Engineering, Sungkyunkwan University (SKKU), Suwon-si, Gyeonggi-do 16419, Republic of Korea.

ACS applied materials & interfaces
|July 29, 2024
PubMed
概括

这项研究引入了一种新的增强等离子体的原子层沉积方法,用于高面比半导体图案中无空隙填充. 优化偏差功率频率可以防止阻断模式的悬架,从而使高级3D设备的自下而上的填充成为可能.

关键词:
在 PEALD,你会发现.偏差的频率偏差的频率这是一个自下而上的,自下而上的体系.填补差距 - 填补差距没有空白的空白.

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相关概念视频

Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
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