在Elitestek Ti60现场可编程门阵列中设计一个高精度的时间转换器
Zongwu He1,2, Xincheng Wen3, Jian Wang1,2
1State Key Laboratory of Particle Detection and Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China.
本研究介绍了FPGA上的高精度时间到数字转换器 (TDC),克服了常见的精度问题. 这种新的设计实现了出色的线性和低误差,用于准确的时间间隔测量.
科学领域:
- 数字电子产品数字电子产品
- 集成电路设计 集成电路设计
- 在FPGA应用程序中.
背景情况:
- 基于现场可编程门阵列 (FPGA) 的时间到数字转换器 (TDC) 提供灵活性,但存在不统一性,延迟线泡和宽延迟单元.
- 这些缺陷降低了TDC精度,并引入了非线性,限制了它们在高精度计时应用中的性能.
研究的目的:
- 在Elitestek Ti60 FPGA上提出和实施一个高精度的TDC架构.
- 为了减轻TDC性能中不均性,延迟线泡和超宽延迟单元的不利影响.
- 为了在时间间隔测量中实现卓越的线性和精度.
主要方法:
- 在Elitestek Ti60 FPGA上实现了一个318级延迟链TDC的设计.
- 在150 MHz的低系统时钟频率上运行TDC.
- 描述了TDC的性能,包括最小显著位 (LSB),微分非线性 (DNL) 和积分非线性 (INL).
主要成果:
- 取得了一个LSB的21.92 ps.
- 在 (-0.976, 1.615) LSB内显示的DNL和在 (-1.446, 2.678) LSB内显示的INL.
- 在各种时间间隔测量中达到14.783 ps的平方根平均误差.
结论:
- 拟议的TDC有效地消除了精度限制因素,如非统一性和延迟线异常.
- 实施的TDC表现出高精度和线性,适合苛刻的计时应用.
- 这项工作推进了基于FPGA的TDC设计,为准确的时间测量提供了强大的解决方案.
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