an-QNA:一种适应性Nesterov近牛顿加速优化的CMOS LNA,用于65nm汽车雷达应用
Unal Aras1, Lee Sun Woo1, Tahesin Samira Delwar1
1Department of Smart Robot Convergence and Application Engineering, Pukyong National University, Busan 48513, Republic of Korea.
Sensors (Basel, Switzerland)
|September 28, 2024
概括
这项研究引入了适应性内斯特罗夫准牛顿加速度 (an-QNA) 优化低噪声放大器 (LNA),以提高线性和更快的收. 通过an-QNA方法,比传统技术提高了电路性能.
科学领域:
- 电气工程 电气工程
- 模拟集成电路设计模拟集成电路设计
背景情况:
- 传统的半牛顿 (c-QN) 电路优化的方法面临着缓慢的融合和局部最小值的挑战.
- 低噪音放大器 (LNA) 是射频 (RF) 系统中的关键组件,需要高线性和低噪音.
研究的目的:
- 提出和优化使用适应性内斯特罗夫准牛顿加速 (an-QNA) 方法的单端至差分两级LNA.
- 通过改进的后线性化 (IPL) 技术来增强LNA的线性.
- 通过二次估计修改,确保优化算法的全球融合.
主要方法:
- 实现一个自适应的内斯特罗夫准牛顿加速 (an-QNA) 优化算法.
- 一个两阶段的单端到差分LNA电路的设计.
- 整合了一种改进的后线性化 (IPL) 技术,以提高线性.
主要成果:
- 模拟性能:17.5dB增益,3.7dB噪声 (NF) 和-13.1dBm 1dB输入压缩点.
- 测量性能:12.9 dB增强,4.98 dB NF,以及-17.8 dBm IP1dB. 测量后的功率为
- 使用65nmCMOS技术实现了0.67mm2的紧芯片面积.
结论:
- 通过an-QNA优化方法,可以显著加速融合,并保证LNA设计的全球融合.
- 拟议的QNA优化的LNA在增益,噪声数字和线性方面表现出了竞争力.
- 该设计为集成电路中的高性能LNA应用提供了可行的解决方案.
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